The present invention is generally directed to charge pumps for use in phase-locked loops (PLLs) and delay locked loops (DLLs), and more specifically, to an integrated circuit that uses switched capacitors to switch on the transistors in a charge pump.
In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits (ICs), such as application specific integrated circuit (ASIC) chips, Radio Frequency Integrated Circuits (RFIC), central processing unit (CPU) chips, digital signal processor (DSP) chips and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices, among other things. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver, cell phone, television receiver, microprocessor, high-speed data transceiver, or the like.
In many integrated circuits, the clock signals that drive an integrated circuit are generated by a frequency synthesizer phase-locked loop (PLL) or a delay locked loop (DLL). PLLs and DLLs are well known to those skilled in the art and have been extensively written about. The dynamic performance of the frequency synthesizer that is used to generated clock signals is dependent on several parameters, including the natural frequency (Fn), the damping factor (DF), the crossover frequency (Fo) and the ratio of the comparison frequency (Fc) to the crossover frequency. The first three parameters depend on the voltage controlled oscillator (VCO) gain (Ko), the F/B (N) divider value, the charge pump current (Ic), and the loop filter components. The last parameter (i.e., the ratio of comparison frequency to crossover frequency) is dependent on the input divider (M) value, as well as the frequency of the input clock itself.
The performance of the frequency synthesizer also depends on the performance of the charge pump located in the PLL or DLL. The charge pump pulse timing jitter and pulse amplitude noise both contribute to synthesizer phase noise. A typical charge pump includes circuitry to avoid what is known as the xe2x80x9cdead zone,xe2x80x9d which occurs at or near the PLL xe2x80x9clockxe2x80x9d state when the phase error is very small and the loop gain would otherwise approach zero. To avoid this problem, both the Pump Up current source and the Pump Down current source of a charge pump are turned on simultaneously for a brief period at the end of each phase detector cycle. However, to reduce charge pump output noise, it is desirable to reduce the ON time of the charge pump outputs in the lock state.
However, reducing the ON time of the charge pump is problematic due to the gate capacitances of the output transistors of the charge pump. Each output transistor is a relatively large device having a proportionately large gate-to-source capacitance (Cgs). Charging and discharging the gate-to-source capacitance (or gate capacitance) increases the delay time for turning the output transistors ON and OFF.
Therefore, there is a need in the art for improved frequency synthesizers for use in generating reference frequency signals. In particular, there is a need in the art for improved charge pumps for use in phase-locked loops or delay-locked loops. More particularly, there is a need for charge pumps that can be turned on and turned off very rapidly.
The present invention provides a charge pump implemented with a pair of CMOS transistors. A P-channel output transistor forms the charging current source and an N-channel output transistor forms the discharging (sinking) current source. Each of the output transistors is turned on by a pre-charged capacitor that is selectively connected to the gate of each output transistor by switch. The pre-charged capacitors are pre-charged to an appropriate over-voltage level by a very low-noise voltage reference circuit. When the switch is turned on, the pre-charged capacitor is suddenly connected to the gate capacitance of the output transistor. The charge on the pre-charge capacitor then flows onto the gate capacitance. The over-voltage on the pre-charge capacitor ensures that the parallel combination of the pre-charged capacitor and the output transistor gate capacitance settles to the proper final Vgs value that cause the proper final drain current. When the switch is turned off, the switch connects the gates of the output transistors to ground, thereby discharging the gate capacitance.
The pre-charged capacitors greatly decrease the delay time for turning on the output transistors. Grounding the gates through the switch decreases the delay time for turning off the output transistors. Thus, the switched capacitor configuration results in much faster output transistor switching times. The faster switching times minimize the amount of time the output transistors are turned on during the lock state, thereby minimizing the contribution of the charge pump to the total output noise of the PLL during the lock state.
Also, the switched capacitor configuration decouples the speed (or bandwidth) requirements of the voltage reference circuits used to pre-charge the pre-charged capacitors from the pump output switching requirements. This allows low-noise circuitry and filtering techniques to be applied to the voltage reference circuits. Also, a digital-to-analog converter (DAC) coupled with appropriate control logic may be used to generate the pre-charge reference voltage. This permits the use of fast PLL lock techniques that modulate loop gain and filter parameters when changing frequencies.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an improved charge pump capable of injecting a charging current onto a loop filter coupled to an output of the charge pump when a Pump Up control signal received by the charge pump is enabled. According to an advantageous embodiment of the present invention, the charge pump comprises: i) a P-channel output transistor capable of injecting the charging current onto the loop filter; ii) a first pre-charge capacitor capable of storing a first pre-charge voltage at least equal to a first desired gate-to-source voltage of the P-channel output transistor; and iii) first switching circuitry capable of coupling the first pre-charge capacitor to a gate of the P-channel output transistor when the Pump Up signal is enabled, such that the first pre-charge voltage turns on the P-channel output transistor and the charging current is adjusted to a final level determined by the first desired gate-to-source voltage.
According to one embodiment of the present invention, the first switching circuitry is capable of discharging the first desired gate-to-source voltage of the P-channel output transistor when the Pump Up control signal is disabled.
According to another embodiment of the present invention, the first switching circuitry discharges the first desired gate-to-source voltage by coupling the gate of the P-channel output transistor to a VDD power supply rail.
According to still another embodiment of the present invention, the charge pump further comprises: iv) a first low noise voltage reference having a first reference voltage output coupled to the first pre-charge capacitor, wherein the first reference voltage output is capable of charging the first pre-charge capacitor to the first pre-charge voltage; and v) a charge pump output control circuit coupled to the first low noise reference and capable of adjusting the first reference voltage output to thereby control the final level of the charging current.
According to yet another embodiment of the present invention, the charge pump further comprises: vi) a P-channel mirror transistor matched to the P-channel output transistor and having a gate coupled to the gate of the P-channel output transistor such that the P-channel mirror transistor and the P-channel output transistor have identical gate to-source voltages and a mirror current of the P-channel mirror transistor mirrors the charging current in the P-channel output transistor by a factor M; and vii) a charging current monitor capable of monitoring the mirror current of the P-channel mirror transistor.
According to a further embodiment of the present invention, the charge pump is capable of sinking a discharging current from the loop filter when a Pump Down control signal received by the charge pump is enabled, the charge pump further comprising: viii) an N-channel output transistor capable of sinking the discharging current from the loop filter; ix) a second pre-charge capacitor capable of storing a second pre-charge voltage at least equal to a second desired gate-to-source voltage of the N-channel output transistor; and x) second switching circuitry capable of coupling the second pre-charge capacitor to a gate of the N-channel output transistor when the Pump Down signal is enabled, such that the second pre-charge voltage turns on the N-channel output transistor and the discharging current is adjusted to a final level determined by the second desired gate-to-source voltage.
According to a still further embodiment of the present invention, the second switching circuitry is capable of discharging the second desired gate-to-source voltage of the N-channel output transistor when the Pump Down control signal is disabled.
According to a yet further embodiment of the present invention, the second switching circuitry discharges the second desired gate-to-source voltage by coupling the gate of the N-channel output transistor to ground.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.